The present invention relates to an internal voltage generating circuit which is capable of producing a stable voltage by reducing a voltage level variation width.
Semiconductor memory devices often use internal voltages generated therein for internal operation, as well as external voltages received from the outside thereof. As an example of internal voltage generating circuits generating the internal voltages, an internal voltage generating circuit configured to generate a voltage (VPP voltage) higher than an external high voltage or a voltage (VBB voltage) lower than an external low voltage (ground voltage) generates a desired voltage by using a charge pump scheme.
FIG. 1 is a block diagram of an internal voltage generating circuit using a conventional charge pump scheme.
Referring to FIG. 1, the internal voltage generating circuit of a conventional semiconductor memory device includes a level detector 10, a ring oscillator 12, a pump control logic 14, and a charge pump 16. The level detector 10 compares a reference voltage VREF with a high voltage VPP provided as a feedback voltage to detect a voltage level at which the high voltage can maintain a constant voltage level. The ring oscillator 12 generates a clock signal OSC for generation of the high voltage VPP, based on an output signal PPE of the level detector 10. The pump control logic 14 controls the generation of the high voltage VPP in response to the clock signal OSC of the ring oscillator 12. The charge pump 16 generates the high voltage VPP under the control of the pump control logic 14.
In the conventional internal voltage generating circuit, when the fed-back high voltage is lower than the reference voltage, the level detector 10 outputs a voltage level detection signal PPE. The voltage level detection signal PPE drives the ring oscillator 12. At the pump control logic 14, the clock signal OSC generated from the ring oscillator 12 is converted into a signal for control of the charge pump 16. When the high voltage VPP provided as a feedback voltage is lower than the reference voltage VREF, the charge pump 16 receives the output signal of the pump control logic 14 and boosts an external power supply voltage VDD to generate the high voltage VPP.
However, the conventional internal voltage generating circuit has the following problems.
FIG. 2 illustrates a variation of a voltage level that is pumped according to a variation of an external power supply voltage VDD in the conventional charge pump scheme.
As the external power supply voltage VDD increases from a voltage VA to a voltage VC, the amount of charges generated per each cycle of the charge pump increases. However, even if the external power supply voltage VDD increases, a certain amount of time is necessary for the level detector 10 to respond. Therefore, when the external power supply voltage VDD has a comparatively high level, an excessive over-pumping section may occur.
FIG. 3 illustrates the actual level of the VPP that is generated to be higher than its target level in the conventional charge pump scheme. The internal voltage generating circuit using the conventional charge pump scheme increases the amount of charges generated by the charge pump as the external power supply voltage VDD increases. Also, a certain amount of time is taken for the VPP level detector to respond, which causes the over-pumped voltage generation.